Itz R NAGA ARJUN

Translating complex algorithms into ultra-efficient hardware architectures, bridging the gap between embedded systems and advanced signal processing.

Discover My Work

About Me

I'm a developer and engineer passionate about the intersection of hardware and software. I am currently pursuing my B.Tech in VLSI Design & Technology at VIT Chennai (CGPA: 8.84, Expected 2028).

My core passion lies in semiconductor design, low-power systems, and bridging ML algorithms with strict silicon constraints. Beyond hardware, I'm an active contributor to the BIS Standards Club and "The White Helmets", solving rigorous algorithmic challenges with over 220+ LeetCode problems resolved.

My Journey

Foundations

RTL to GDS Design

Completed intensive training in full chip design flow via NPTEL, mastering RTL design, synthesis, and physical layout.

Algorithms

Signal & Voice Processing

Dove deeply into DSP concepts, discovering innovative ways hardware acceleration solves complex Voice AI challenges.

VLSI Research Intern

CNVD, VIT Chennai

Simulating VLSI CNN implementations with Cross-Sim, focusing heavily on power-efficient in-memory architectures.

VLSI CNN In-Memory

Case Study

Featured Research

Acoustic Transfer Function Estimation

Problem:

In my work on adaptive signal processing, accurately estimating the transfer function in both near-field and far-field acoustic environments presented a major challenge, leading to significant mismatch errors.

Process & Solution:

I am developing a novel, distance-based model selection algorithm to dynamically switch between estimation models. This work, which I am implementing on an FPGA for real-time, low-power processing, forms the basis of a paper idea focusing on efficient hardware implementations.

Python Signal Processing FPGA / Verilog

Technical Expertise

SystemVerilog

Verilog

RISC-V Assembly

8051 Assembly

8086 Assembly

C & C++

Java

Python

Perl & TCL

Embedded C

Cadence Virtuoso

TCAD

CrossSim

Xilinx Vivado

Linux

ModelSim

RTL Design

RTL to GDS II

Signal Processing

HW-SW Co-design

Projects Done

100-Days-of-SystemVerilog RTL Design Sprint

Executed an intensive RTL design sprint focused on mastering production-grade SystemVerilog. Implemented advanced architectural concepts including complex Clock Domain Crossing (CDC) modules and open source verification methodologies for ASIC/FPGA workflows.

SystemVerilog CDC Design ASIC / FPGA

SGMSE+ Generative Speech Enhancement

Engineered a Score-Based Diffusion Model pipeline on Single-GPU architecture. Solved PyTorch 2.6 security blocks and managed CUDA kernel JIT compilation. Optimized model checkpoints (66% size reduction) and implemented CCA to correct metrics to -2.7dB.

Generative AI PyTorch & CUDA Signal Processing

Parameterized Structural Verilog Generator

Authored an automated Perl-based EDA scripting tool to dynamically synthesize structural Verilog code. Accelerated hardware design workflows by auto-generating complex hybrid adders, N×N multipliers, and N-tap FIR filters.

Perl Verilog Synthesis EDA Automation

AJJU Voice-Controlled Security Assistant

Built a multi-threaded voice command engine using Python. Integrated OS-level subprocess management to execute shell commands, open applications, and perform web scraping based on Natural Language triggers.

Python OS Integration NLP

Reliability Optimization of 650V GaN-on-Si HEMTs

Conducted extensive TCAD simulations to analyze and optimize the reliability of High Electron Mobility Transistors for EV fast-charging applications. Investigated device physics to mitigate degradation factors in high-power semiconductor environments.

TCAD Simulation Semiconductor Physics Power Electronics

Pac-Man & Game History

Developed a modular Pac-Man clone using OOP natively in Python & Pygame. Implemented collision detection and A* search logic for ghost movement, and integrated a MySQL relational database to persistently store user sessions.

Python (OOP) MySQL Game Algorithms

Glitch Filter Design in Cadence Virtuoso

Designed and simulated a robust glitch filter utilizing D-Flip Flops (DFFs) within Cadence Virtuoso. Gained hands-on experience with schematic entry, simulation, and resolving signal integrity issues at the transistor level.

Cadence Virtuoso Transistor Level Signal Integrity

4-bit RISC Processor Simulator

Modeled the Fetch-Decode-Execute cycle of a Von Neumann architecture using C++. Simulated the ISA, including the Program Counter, ALU logic, and Register File interactions within an embedded environment.

C++ Computer Arch ISA Design

Adaptive Power Management System

Implemented an FSM in C++ to model VLSI power gating techniques. Optimized system energy by dynamically handling ISRs from sensors to toggle peripheral clock domains seamlessly.

C++ State Machines Low-Power Logic

Achievements & Leadership

01. Multiple Hackathon Wins

Participated in numerous hackathons, consistently securing top competitive placements by rapidly prototyping complex hardware and software solutions under strict time constraints.

02. 2nd Place, Circuit Debugging

Demonstrated rapid analytical problem-solving and deep hardware comprehension to secure 2nd place in a highly competitive technical debugging contest.

03. Algorithmic Problem Solver

Deeply engaged in competitive programming and continuous skill development, actively solving technical challenges including 220+ rigorous algorithmic problems on LeetCode.

Get In Touch

I'm actively seeking new opportunities and am always open to collaborations. Let's connect!